1. Field of the Invention
The present invention relates generally to a method of forming dual-metal gates in a semiconductor device, and more particularly, to a method of forming dual-metal gates in a semiconductor device using a damascene process.
2. Description of the Related Art
Lately, as development of a sub-0.1 xcexcm MOSFET device progresses, a gate having low resistance is the major issue for securing device characteristics. Thus, many efforts are made to develop a metal gate as a substitute for the previous polysilicon or transition metal silicide gate.
Specifically, a gate in a MOSFET device is formed of polysilicon to sufficiently satisfy the gate-requiring physical properties such as high melting point, and to decrease difficulty in film formation and in line pattern, stability for oxidation ambience, surface planarization and the like. Moreover, in an actual MOSFET device, a polysilicon gate containing dopants such as P, As, B or the like realizes the low resistance.
However, gate width, gate insulating layer thickness, junction depth and the like are eventually reduced as the integration of a semiconductor is highly increased. Thus, polysilicon fails to further realize the low resistance required for the critical dimension.
In the mean time, developments for new gate material as a substitute for polysilicon progresses are necessitated. In the early days, the research and developments are focused on a polycide gate using transition metal silicide material. Yet, the polycide gate still contains a polysilicon content resulting in difficulty in realizing low resistance. Namely, the polysilicon content in the polysilicide gate brings about the increasing effective thickness of a gate insulating layer due to gate depletion effect, threshold voltage variance due to boron penetration/dopant distribution fluctuation in a p+ doped polysilicon gate and the like, thereby producing a limitation to realize low resistance therein.
Research and development for the metal gate addressing the above disadvantages is required badly.
Boron penetration and gate depletion do not arise in a metal gate using no dopant. Moreover, the metal gate has a work function value corresponding to a mid-band gap of silicon, thereby being applied to a single gate enabling the formation of symmetric threshold voltage in NMOS and PMOS areas. In this case, W, WN, Ti, TiN, Mo, Ta, TaN and the like are the metals of which work function values correspond to the mid-gap of silicon.
If a CMOS device including the single gate is fabricated using a metal gate, flat band voltage of the device in NMOS and PMOS areas is reduced. Thus, threshold voltage is increased. In order to reduce the threshold voltage, a buried channel should be formed using counter doping. Yet, in such a case, the short channel effect of a MOSFET device is increased, threshold voltage is decreased, DIBL (drain induced barrier lowering) and the like are brought about.
Therefore, the latest research and development is carried out on forming a dual-metal gate in a manner that metal gates having different work function values are formed in the NMOS and PMOS areas respectively using the operation principle of a dual-polysilicon gate.
It is ideal for forming a dual-metal gate that Fermi energy value of a metal gate in NMOS area exists near a conduction band of silicon while that of the other metal gate in PMOS area exists near a valence band of silicon.
A method of forming dual-metal gates in a semiconductor device according to the prior art is explained by referring to FIG. 1A to FIG. 1E as follows.
FIGS. 1A to 1E illustrate cross-sectional views of forming gates in a semiconductor device according to the prior art.
Referring to FIG. 1A, a semiconductor substrate 1, having a field oxide layer 2, is provided. An N well 3a and a P well 3b are formed respectively in the semiconductor substrate 1 using masking and ion implantation processes known in the art. A screen oxide layer (not shown in the drawing) of a film is formed on the semiconductor substrate 1. Ion implantations known in the art for adjusting threshold voltage are then carried out on the N well 3a and P well 3b areas respectively.
Referring to FIG. 1B, after the screen oxide layer has been removed, a gate insulating layer 4, a PMOS metal layer 5, and a barrier layer 6 are formed on the semiconductor substrate 1 including the field oxide layer 2, sequentially. The PMOS metal layer 5 is formed of a metal material of which the Fermi energy lies near a valence band of silicon.
Referring to FIG. 1C, a mask pattern (not shown in the drawing) covering the PMOS area is formed on the barrier layer 6. Then, the barrier layer 6 and PMOS metal layer 5 in the exposed NMOS area are etched.
Referring to FIG. 1D, an NMOS metal layer 7 is formed over an entire surface of the semiconductor substrate 1. A mask nitride layer 8 is then formed on the NMOS metal layer 7. In this case, the NMOS metal layer 7 is a metal material of which the Fermi energy lies near a conduction band of silicon.
Referring to FIG. 1E, etched by the process known in the art are the mask nitride layer 8/NMOS metal layer 7/gate insulating layer 4 in the NMOS area and the mask layer 8/NMOS metal layer 7/barrier layer 6/PMOS metal layer 5/gate insulating layer 4 in the PMOS area. As a result of this etch, metal gates 10a and 10b are formed on the P well 3a and the N well 3b, respectively. A spacer nitride layer is deposited over an entire area of the semiconductor substrate 1. Spacers 9 are then formed on both sidewalls of the respective metal gates 10a and 10b by blanket-etching the nitride layer. Source/drain regions 11a and 11b are formed on later side of the respective metal gates 10a and 10b by carrying out source/drain ion implantation on the resulting structure having undergone the above steps. Consequently, a CMOS device including dual-metal gates is fabricated.
Unfortunately, the CMOS device including the dual-metal gates according to the related has problems or disadvantages, as follows.
First, when the dual-metal gates are formed by the prior art, the respective metal layers in the NMOS and PMOS areas are etched by RIE (reactive ion etch). Because the heights and materials of the respective metal gates in the NMOS and PMOS areas are different from each other, it is difficult to set up an etch recipe. Thus, if the recipe setup is wrong, poor etching may result in the NMOS area of which etch depth is relatively deep as well as substrate damage in the PMOS area of which etch depth is relatively shallow.
Second, when the dual-metal gate is formed by the prior art, plasma damages in the etching and ion implantation processes and thermal damage caused by a thermal process after the gate formation result, thereby reducing device characteristics.
Third, when the barrier layer and NMOS metal layer are etched in the PMOS area, the gate insulating layer in the PMOS area is damaged by the etch, thereby reducing GOI (gate oxide integrity) characteristics.
Accordingly, the present invention is directed to a method of forming dual-metal gates in a semiconductor device that substantially obviates one or more of the problems due to limitations and disadvantages of the prior art.
The object of the present invention is to provide a method of forming dual-metal gates in a semiconductor device enabling to overcome the difficulty in establishing an etch recipe.
Another object of the present invention is to provide a method of forming dual-metal gates in a semiconductor device so as to prevent plasma damage in the etching and ion implantation processes and thermal damage caused by a thermal process.
A further object of the present invention is to provide a method of forming dual-metal gates in a semiconductor device enabling prevention of GOI (gate oxide integrity) characteristic degradation.
Another further object of the present invention is to provide a method of forming dual-metal gates in a semiconductor device to overcome the above-mentioned problems or disadvantages using a damascene process.
Additional features and advantages of the invention will be set forth in the description which follows, and in part will be apparent from the description, or may be learned by practice of the invention. The objectives and other advantages of the invention will be realized and attained by the structure particularly pointed out in the written description and claims hereof, as well as the appended drawings.
To achieve these and other advantages, and in accordance with the purpose of the present invention as embodied and broadly described, a method of forming dual-metal gates according to the present invention includes the steps of providing a semiconductor substrate having a PMOS area and an NMOS area wherein dummy gates are formed in the PMOS and NMOS areas respectively, forming an insulating interlayer on the semiconductor substrate so as to cover the dummy gates, polishing the insulating interlayer until the dummy gates are exposed, forming a first groove defining a first metal gate area by selectively removing one of the dummy gates formed in the PMOS and NMOS areas, forming a first gate insulating layer and a first metal layer on an entire area of the semiconductor substrate including the first groove successively, forming a first metal gate in the first groove by etching the first metal layer and first gate insulating layer until the insulating interlayer is exposed, forming a second groove defining a second metal gate area by removing the remaining dummy gate, forming a second gate insulating layer and a second metal layer on the entire area of the semiconductor substrate including the second groove, and forming a second metal gate in the second groove by etching the second metal layer and second gate insulating layer until the insulating interlayer is exposed.
In another aspect of the present invention, a method of forming dual-metal gates includes the steps of providing a semiconductor substrate having a PMOS area and an NMOS area wherein dummy gates are formed in the PMOS and NMOS areas respectively, forming an insulating interlayer on the semiconductor substrate so as to cover the dummy gates, polishing the insulating interlayer until the dummy gates are exposed, forming first and second grooves defining first and second metal gate areas, respectively, by removing the dummy gates, successively forming a gate insulating layer and a first metal layer on an entire area of the semiconductor substrate including the first and second grooves, selectively forming a metal nitride layer by carrying out nitridation on the first metal layer formed in one of the PMOS and NMOS areas, forming a second metal layer on the metal nitride layer and the first metal layer so as to fill up the first and second grooves, and forming first and second metal gates in the PMOS and NMOS areas, respectively, by etching the second metal layer, first metal layer, metal nitride layer, and gate insulating layer until the insulating interlayer is exposed.
It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory and are intended to provide further explanation of the invention as claimed.